1. Field of Invention
The present invention relates to a semiconductor device, an electro-optical device substrate, a liquid crystal device substrate and a manufacturing method therefor, a liquid crystal device, and an electronic apparatus using the liquid crystal device. Particularly, the present invention relates to a technique for protecting circuits and elements on a substrate from static electricity produced in the process for manufacturing a liquid crystal device substrate and electric charge accumulated on the surface of an insulating substrate.
2. Description of the Related Art
In a liquid crystal cell which constitutes a liquid crystal device, for example, a plurality of data lines and a plurality of scanning lines are formed in a lattice form, and an active substrate and a counter substrate are disposed with a predetermined space therebetween. On the active matrix substrate, pixel electrodes, thin film transistors (abbreviated to xe2x80x9cTFTxe2x80x9d hereinafter) serving as pixel electrode drive switching elements, and the like are arranged in a matrix. On the counter substrate, a counter electrode, and the like are arranged. The active matrix substrate and the counter substrate are combined together by a sealing material containing a spacer so that the electrode formation surfaces thereof are opposed to each other with a predetermined space therebetween. A liquid crystal is sealed between both substrates.
In manufacturing the active matrix substrate having the above construction, TFTs are formed by using a semiconductor manufacturing process. However, in some cases, the substrate is charged with static electricity during the many steps of the manufacturing process, and electric charge is accumulated on the surface of the substrate due to the influence of the plasma processing step, or the like. Particularly, in the active matrix substrate for a liquid crystal device using an insulating substrate made of glass, quartz, or the like, there is no escape for the charged static electricity and accumulated charge, and thus defects such as electrostatic damage to TFTs, characteristic failures, etc. occur due to the presence of the static electricity and electric charge in some cases.
Therefore, a measure is taken in which wiring as a measure for static electricity is provided along the periphery of the substrate, and short-circuit wiring is formed to electrically connect signal lines such as scanning lines and data lines in the course of the manufacturing process so that the static electricity produced in the manufacturing process and electric charge are diffused to the wiring as the measure for static electricity in the periphery of the substrate through the short-circuit wiring, preventing unexpected excessive current due to the static electricity and electric charge from flowing into the internal TFTs, etc. Although the short-circuit wiring is required for protecting the elements such as the TFTs and wiring from static electricity in the course of the manufacturing process, the short-circuit wiring is not required after the manufacturing process. In addition, since inspection cannot be performed in a state wherein the signal lines are short-circuited in the step of inspecting electric properties, and the like, the short-circuit wiring must be cut by any method after the completion of the manufacturing process.
Therefore, the applicant proposed the method of forming and cutting short-circuit wiring disclosed in Japanese Unexamined Patent Publication No. 11-95257. This method is a method in which short-circuit wiring is formed and cut at the same time as the step of depositing any of various films, patterning, forming contact holes, etching, or the like, and is thus an excellent method because a special step for forming and cutting the short-circuit wiring need not be added. The construction of short-circuit wiring and the method of forming and cutting it disclosed in the above publication will be described below with reference to the drawings.
FIG. 2 is a schematic drawing of the construction of an active matrix substrate. As shown in this figure, in the active matrix substrate 7, a plurality of scanning lines 4 and a plurality of data lines 3 are provided on an insulating substrate 12 so as to cross each other, and pixels 8 are formed in a matrix in the respective regions partitioned by the scanning lines 4 and the data lines 3. The scanning lines 4 may be made of a polycrystalline silicon film, and the data lines 3 may be made of a metal film of aluminum or the like. The region where a plurality of pixels 8 are formed in a matrix is a pixel region 9 (image display region). In the periphery of the pixel region 9, a data line driving circuit 10 is formed for supplying image signals to the plurality of data lines 3, and scanning line driving circuits 11 are formed at both ends of the scanning lines 4, for supplying scanning signals for image selection to the scanning lines 4.
In the active matrix substrate 7, as a measure for static electricity, first short-circuit wiring 41 is formed for electrically connecting all signal wiring 16 and 17. Also, second short-circuit wiring 42 is formed for electrically connecting all scanning lines 4. Furthermore, third short-circuit wiring 43 is formed for electrically connecting all data lines 3. All short-circuit wiring 41, 42 and 43, which may be made of a polycrystalline silicon film of the same layer as the scanning lines 4, are electrically connected to each other. In FIG. 2, positions marked with xe2x80x9cxxe2x80x9d in the course of each of the short-circuit wiring 41, 42 and 43 is a cutting portion where each of the short-circuit wiring 41, 42 and 43 is cut after use.
FIG. 34 is an enlarged plan view showing the corner of a pixel region 9 of an active matrix substrate 7. As shown in this figure, pixel switching TFTs 2 are respectively provided in the pixels 8 to be connected to the scanning lines 4 and the data lines 3, and capacitance lines 6 are extended over a plurality of the pixels 8. As shown in FIGS. 43(A)-(C) which will be referred to below, each of the TFTs 2 may include a gate electrode 20 formed integrally with the scanning lines 4, and a semiconductor active film 27 which may include source regions 25a and 25b electrically connected to the data line 3 through a source contact hole 23, which passes through a first interlayer insulating film 21, and drain regions 26a and 26b electrically connected to a pixel electrode 1 through a drain contact hole 24 which passes through the first interlayer insulating film 21 and a second interlayer insulating film 22. The second short-circuit wiring 42 for electrically connecting the scanning lines 4, and the third short-circuit wiring 43 for electrically connecting the data lines 3 are formed as shown in FIG. 34. In this drawing, reference numeral 37 denotes a cutting portion of each of the short-circuit wiring 42 and 43, specifically a hole pattern (referred to as a xe2x80x9ccutting holexe2x80x9d hereinafter) passing through the first interlayer insulating film 21 and the second interlayer insulating film 22.
FIG. 35 is a plan view showing the connecting structure between signal wiring and short-circuit wiring in the active matrix substrate 7 shown in FIG. 34. As shown in this figure, signal wiring 16 and 17 which may be made of a metal film of aluminum or the like, and are located in a layer different from the first short-circuit wiring 41. Therefore, the signal wiring 16 and 17 are electrically connected to the first short-circuit wiring 41 through contact holes 34 passing through the first interlayer insulating film 21 located therebetween. This connecting structure applies to the data lines 3, i.e., the data lines 3 are electrically connected to the third short-circuit wiring 43 through the contact holes 34 passing through the first interlayer insulating film 21 located therebetween. Like the second short-circuit wiring 42 and the third short-circuit wiring 43, the cutting holes 37 are provided in the course of the first short-circuit wiring 41.
FIG. 36 is a plan view showing the terminal area of the active matrix substrate 7. As shown in FIG. 36 and FIGS. 43(A)-(C) which will be referred to below, each of terminals 30 may include a pad exposed in each aperture 22a of the second interlayer insulating film 22, and can be connected to an external terminal. The terminals 30 are formed in a layer above the first interlayer insulating film 21. On the other hand, short-circuit wiring 33 for electrically connecting the plurality of the terminals 30 is formed in a layer below the first interlayer insulating film 21 at the same time as the scanning lines 4, and thus terminal under sheet films 31 which constitutes portions of the short-circuit wiring 33 are electrically connected to the terminals 30 through the contact holes 32 formed in the first interlayer insulating film 21. The cutting holes 37 are also provided in the course of the short-circuit wiring 33.
Next, the method of manufacturing the active matrix substrate 7 having the above construction is described with reference to FIGS. 37(A)-(C) to 43(A)-(C). These figures are drawings showing the steps of the exemplary method of manufacturing the active matrix substrate 7, where FIGS. 37(A) to 43(A) are sectional views taken along line 37A-37Axe2x80x2 of FIG. 34 (sectional views of the pixel TFT area), FIGS. 37(B) to 43(B) are sectional views (sectional views of the electrostatic measure wiring area including the cutting portions of the short-circuit wiring) taken along line 37B-37Bxe2x80x2 of FIG. 35, and FIGS. 37(C) to 43(C) are sectional views (sectional views of the terminal area) taken along line 37C-37Cxe2x80x2 of FIG. 36. The active matrix substrate 7 is an example of so-called polysilicon TFT-type active matrix substrates using a polycrystalline silicon film as the semiconductor active film 27 of each TFT 2.
First, as shown in FIGS. 37(A)-(C), a polycrystalline silicon film 78 is formed on the surface of the insulating substrate 12, such as a glass substrate. As shown in FIGS. 38(A)-(C), the polycrystalline silicon film 78 is then patterned to form the island-like semiconductor active films 27 in the pixel TFT area. On the other hand, in the electrostatic measure wiring area and the terminal area, the polycrystalline silicon film 78 is completely removed. Next, gate oxide films 65 are formed on the surface of the semiconductor active films 27 by using a thermal oxidation method. Then, a conductive polycrystalline silicon film is formed over the entire surface, and then patterned to form gate electrodes 20 in the pixel TFT area. On the other hand, in the electrostatic measure wiring area and the terminal area, the polycrystalline silicon film is left as the short-circuit wiring 33 (corresponding to the first, second and third short-circuit wiring 41, 42 and 43) and the terminal under sheet films 31.
Next, as shown in FIGS. 39(A)-(C), the source regions 25a and 25b, and the drain regions 26a and 26b are formed in the semiconductor active films 27 by an ion implantation method, and then the first interlayer insulating film 21 is formed over the entire surface. Next, the source contact holes 23 and the contact holes 32 are formed in the portions, of the first interlayer insulating film 21, which correspond to the source regions 25b in the pixel TFT area, and the terminal under sheet films 31 in the terminal area, respectively. Next, a metal film of an aluminum film or the like is deposited over the entire surface, and then patterned to form source electrodes 73 as portions of the data lines 3 in the pixel TFT area. At the same time, signal wiring 74 is formed in the electrostatic measure wiring area, and the terminals 30 are formed in the terminal area. In the above-described steps, the first and third short-circuit wiring 41 and 43 are connected to the signal wiring 16 and 17 and the data lines 3.
Next, as shown in FIGS. 40(A)-(C), the second interlayer insulating film 22 is formed over the entire surface. Then, the drain contact holes 24 are formed in the portions of the first interlayer insulating film 21 and the second interlayer insulating film 22, which correspond to the drain regions 26b, in the pixel TFT area. At the same time, in the electrostatic measure wiring area, the cutting holes 37 are formed above the short-circuit wiring 33 to pass through the first interlayer insulating film 21 and the second interlayer insulating film 22.
Next, an indium tin oxide (referred to as xe2x80x9cITOxe2x80x9d hereinafter) film is deposited over the entire surface, and then patterned to form the pixel electrodes 1 in the pixel TFT area, as, shown in FIGS. 41(A)-(C). On the other hand, in the electrostatic measure wiring area and the terminal area, the ITO film is completely removed.
Next, as shown in FIGS. 42(A)-(C), a resist mask 76 having apertures in regions to be exposed as the terminals 30 in the terminal area is formed on the second interlayer insulating film 22. The resist mask 76 covers the whole pixel TFT area, and has apertures at positions corresponding to the cutting holes 37 in the electrostatic measure wiring area. In the electrostatic measure wiring area, the apertures of the resist mask 76 are larger than the cutting holes 37.
Then, etching is performed by using the resist mask 76 to expose the terminals 30 from the apertures 22a of the second interlayer insulating film 22 in the terminal area, as shown in FIGS. 43(A)-(C). Then, in the electrostatic measure wiring area, the short-circuit wiring 33 is cut to electrically separate the wiring from each other.
In this way, the above-described method is capable of forming the short-circuit wiring 33 at the same time as the formation of the scanning lines 4 and the gate electrodes 20 so that in short-circuiting wiring located in a layer different from the short-circuit wiring 33, as in the data lines 3 and the signal wiring 74 (16, 17), contact holes are formed at the same time as the formation of the source contact holes 23 of the TFTs 2 so that the data lines 3 and the signal wiring 74 can be electrically connected to the short-circuit wiring 33.
The method of cutting the short-circuit wiring 33 is described in detail below. As separately shown in FIG. 44(A), the second interlayer insulating film 22 is formed, and then the cutting holes 37 are formed at positions above the short-circuit wiring 33 to pass through the first interlayer insulating film 21 and the second interlayer insulating film 22 at the same time as the formation of the drain contact holes 24 of the TFTs 2. Then, the pixel forming ITO film formed above these holes is removed, and then the photolithography step is carried out to expose the terminals of the terminal areas. However, in the resist mask 76, the apertures are formed not only above the terminals but also above the cutting holes 37. This is because it is desired to perform subsequent etching for cutting the short-circuit wiring by using the resist mask 76 without increasing the photolithography step. Then, the second interlayer insulating film 22 is etched to expose the terminals. Usually, as the etching, only wet etching is employed, or a method which may include dry etching to some extent, and then wet etching is frequently employed. This is because an insulating substrate is used as an active matrix substrate, particularly for a liquid crystal display, and it is thus desired to avoid the accumulation of charge due to exposure of the surface of the substrate to plasma in dry etching.
Therefore, a silicon oxide film type insulating film is generally used as the second interlayer insulating film 22, and thus the second interlayer insulating film 22 deposited above the terminals is etched with an etchant capable of etching the silicon oxide film. At the same time, even if a native oxide film is formed on the surface of the polycrystalline silicon film which constitutes the short-circuit wiring 33 exposed from the cutting holes 37, the native oxide film is etched to create the state in which the surface of the short-circuit wiring 33 is slightly over-etched, as shown in FIG. 44(B). The removal of the native oxide film has the effect of ensuring etching of the polycrystalline silicon film, which constitutes the short-circuit wiring, in the next step of cutting the short-circuit wiring. Then, as shown in FIG. 44(C), the polycrystalline silicon film exposed from the cutting holes 37 is etched by dry etching or the like to securely cut the short-circuit wiring 33 at these positions.
In recent years, a liquid crystal display has been increasingly required to have higher function and higher performance, and TFT used for an active matrix substrate has been required to have higher-speed performance. In this case, the conversion of polycrystalline silicon conventionally used as a semiconductor active film material for TFT, which greatly influences the operation speed, to single crystal silicon has been studied. In the field of the semiconductor manufacturing process, the SOI (Silicon On Insulator) technique of forming a single crystal silicon thin film on an insulating film is conventionally known, and a SIMOX (Separation by Implanted Oxygen) technique, a wafer laminating technique, and the like are used as means for manufacturing SOI wafers. Particularly, an SOI wafer manufactured by the wafer laminating technique is preferred from the viewpoints of the good crystallinity of an SOI layer, and the wide range of material selection permitting the use of a transparent material for a support substrate. Therefore, in realizing a single crystal silicon TFT, an SOQ (Silicon On Quartz) substrate produced by the bonding method is studied as a selection of material for the active matrix substrate for a liquid crystal display.
However, in actually manufacturing the active matrix substrate by using the SOQ substrate produced by the bonding method, the use of the electrostatic protecting measure produces the problems below. In the SOQ substrate produced by the bonding method, a single crystal silicon substrate which may include a silicon oxide film formed on the surface thereof by a thermal oxidation method, and a quartz substrate are combined by heat treatment with the silicon oxide film side adhering to the quartz substrate, and thus an interface (referred to as a xe2x80x9cbonding interfacexe2x80x9d hereinafter) having relatively weak crystal bonding is present between the silicon oxide film and the quartz substrate.
In use of the SOQ substrate, the sectional structure in the step of cutting the short-circuit wiring is as shown in FIG. 26(B). Namely, as shown in this figure, a buried oxide film 62 which may include a silicon oxide film is bonding on a quartz substrate 63, the interface between the quartz substrate 63 and the buried oxide film 62 being the bonding interface. Then, the short-circuit wiring 33 is formed on the buried oxide film 62, and the cutting holes 37 for exposing the short-circuit wiring 33 are formed in the first interlayer insulating film 21 and the second interlayer insulating film 22 bonding in turn on the buried oxide film 62. In this sectional structure, according to the above-described procedure, the second interlayer insulating film 22 is first etched for exposing the terminals of the terminal areas. In the use of the bonding SOQ substrate, the buried oxide film 62 including a silicon oxide film serves as a base of the short-circuit wiring 33, and is thus etched at the same time as the second interlayer insulating film 22. The thickness of the buried oxide film 62 is in the range of, for example, several tens nm to several nm according to the type of the SOQ substrate, but a film of several hundreds nm is frequently used. In this case, the thickness of the buried oxide film 62 is significantly smaller than the thickness of the second interlayer insulating film 22 in some cases.
Under these conditions, when the second interlayer insulating film 22 is etched until the terminals are exposed, the buried oxide film 62 below the short-circuit wiring 33 is completely etched in the course of etching so that the etchant reaches the bonding interface. However, the structure shown in FIGS. 40(A)-(C) causes no problem because the interface between the substrate and the insulating film bonding thereon is strong, while the SOQ substrate having the bonding interface causes a problem in which the etchant easily permeates because the weak crystal bonding of the bonding interface, as described above, thereby etching the buried oxide film 62 to deeply cut it along the bonding interface, as shown in FIG. 26(B). This state causes a problem in which cracks C occur in the insulating film over a region including the buried oxide film 62, the first interlayer insulating film 21 and the second interlayer insulating film 22, and extreme cases, the insulating film peels in the cracked portions.
In order to avoid at least this problem, dry etching is possibly used for etching the second interlayer insulating film so as to prevent the etchant from permeating along the bonding interface. However, dry etching is undesirable because electric charge is accumulated on the surface of the substrate, and damage occurs due to plasma. In another possible method, the second interlayer insulating film is etched in different steps in the terminal area and the electrostatic measure wiring area. In this case, the number of the steps is increased, which may undesirably deteriorate the advantage of the method capable of forming and cutting short-circuit wiring while preventing the complication of a method as much as possible. Even when a complete electrostatic measure is taken, the measure is meaningless when it complicates the manufacturing process to significantly increase the manufacturing cost and TAT (Turn Around Time, the time from start work to the completion of a product).
The present invention has been achieved for solving at least the above problems, and one object of the present invention is to provide methods and systems for securely preventing cracking and peeling of an insulating film in the periphery of a cutting portion in cutting short-circuit wiring by etching in a substrate used for various electronic devices such as a liquid crystal device, an electro-optical device, or a semiconductor device in which an electrostatic measure is taken by the above-described short-circuit wiring. Another object of the present invention is to provide methods and systems for preventing complication of a conventional manufacturing process as much as possible in preventing cracking and peeling of the insulating film.
A semiconductor device of an exemplary embodiment of an exemplary embodiment of the present invention may include a substrate, a base oxide film provided on the substrate, a plurality of signal lines, and short-circuit wiring provided on the base oxide film for electrically connecting the plurality of signal lines during a manufacturing process. A hole is provided in an insulating film covering the short-circuit wiring for cutting the short-circuit wiring by etching to release the signal lines from a short-circuit state. An etching stop layer is provided in a region wider than at least the hole between the short-circuit wiring and the base oxide film, and may include a film having resistance to etching of an oxide film formed on the surface of the short-circuit wiring.
An electro-optical device substrate of an exemplary embodiment of the present invention may constitute one of a pair of substrates of an electro-optical device in which an electro-optical material is held between the pair of substrates. The electro-optical device substrate may include a substrate, a base oxide film provided on the substrate, a plurality of signal lines, and short-circuit wiring provided on the base oxide film, for electrically connecting the plurality of signal lines during a manufacturing process. A hole is provided in an insulating film covering the short-circuit wiring for cutting the short-circuit wiring by etching to release the signal lines from a the short-circuit state. An etching stop layer is provided in a region wider than at least the hole between the short-circuit wiring and the base oxide film, and may include a film having resistance to etching of an oxide film formed on the surface of the short-circuit wiring.
A liquid crystal device substrate of an exemplary embodiment of the present invention may constitute one of a pair of substrates of a liquid crystal device in which a liquid crystal is held between the pair of substrates. The liquid crystal device substrate may include a substrate, a base oxide film provided on the substrate, a plurality of signal lines, and short-circuit wiring provided on the base oxide film for electrically connecting the plurality of signal lines during a manufacturing process. A hole is provided in an insulating film covering the short-circuit wiring for cutting the short-circuit wiring by etching to release the signal lines from a short-circuit state. An etching stop layer is provided in a region wider than at least the hole between the short-circuit wiring and the base oxide film, and may include a film having resistance to etching of an oxide film formed on the surface of the short-circuit wiring.
It should be understood that although xe2x80x9celectrically connecting the plurality of signal lines in a manufacturing stepxe2x80x9d may be described to clarify the function of xe2x80x9cshort-circuit wiringxe2x80x9d, xe2x80x9cshort-circuit wiringxe2x80x9d is not used only for a measure for static electricity. As described above, xe2x80x9cshort-circuit wiringxe2x80x9d may be used for allowing electric charge escape on the substrate due to various causes, such as static electricity produced in the manufacturing process and accumulated charge in plasma processing.
In various exemplary embodiments of the present invention, xe2x80x9ca film having resistance to etching of an oxide filmxe2x80x9d may mean a film which has some extent of selectivity to etching of the oxide film, and which may be partially etched under the etching conditions of the manufacturing process as long as the film is not completely etched with the base not etched.
In the structure in which the short-circuit wiring is formed directly on the base oxide film, etching as pre-treatment for removing the oxide film formed on the surface of the short-circuit wiring during cutting of the short-circuit wiring causes etching of the base oxide film to excessively progress etching due to permeation of the etchant into the interface between the substrate and the base oxide film, thereby cracking or peeling the insulating film. On the other hand, in the structure of the various exemplary embodiments of the present invention, the etching stop layer is interposed between the short-circuit wiring and the base oxide film, and thus etching of the oxide film formed on the surface of the short-circuit wiring is stopped in the etching stop layer because the etching stop layer has resistance to etching of the oxide film, preventing the base oxide layer from being etched. In addition, the structure of the present invention causes no trouble in the subsequent step of cutting the short-circuit wiring. It is thus possible to securely prevent the occurrence of cracking and peeling of the insulating film accompanying the step of cutting the short-circuit wiring. It should be appreciated that the present invention is not limited to a liquid crystal display substrate, and can also be applied to various electronic devices such as a semiconductor device, or an electro-optical device. The use of the present invention can realize an electronic device having high reliability and high performance.
Although the etching stop layer may be exclusively separately formed, the etching stop layer is preferably rationally formed by using an arbitrary film used in a layer below the short-circuit wiring and used at positions other than the short-circuit wiring forming positions in order to prevent complication of the manufacturing process.
In an application of the various exemplary embodiments of the present invention to a liquid crystal display substrate, for example, a TFT array substrate using TFTs as pixel switching elements, a semiconductor active film which constitutes source regions, drain regions, channel regions, etc. of the TFTs generally may include a silicon film. In this case, preferably, the etching stop layer may include the silicon film in the same layer as the semiconductor active film, and the short-circuit wiring is made of the gate electrode material of the TFTs.
In this construction, the etching stop layer and the short-circuit wiring can be formed at the same time as the formation of the TFTs.
In this case, the insulating film which constitutes the gate insulating films of the TFTs is further interposed between the short-circuit wiring and the etching stop layer.
When the etching stop layer has conductivity, even if the short-circuit wiring is cut, contact between the short-circuit wiring and the etching stop layer short-circuits the cut portions of the short-circuit wiring through the etching stop layer, thereby possibly substantially failing to cut the short-circuit wiring. However, the above-described construction enables reliable cutting of the short-circuit wiring because the insulating film, which constitutes the gate insulating films of the TFTs, is interposed between the short-circuit wiring and the etching stop layer.
As the silicon film used for the semiconductor active films of the TFTs, any one of a polycrystalline silicon film, an amorphous silicon film, and a single crystal silicon film may be used. However, the use of the single crystal silicon film having high carrier mobility among these films permits an attempt to increase the operation speed of the TFTs. In use of the single crystal silicon film, the bonding SOI substrate having the bonding interface between the substrate and the base oxide film can be used as a raw material substrate for the substrate, the base oxide film and the single crystal silicon film.
Some methods of depositing the base oxide film have a problem in which the etchant permeates into the interface between the substrate and the base oxide film. However, when the bonding SOI substrate having the bonding interface between the substrate and the base oxide film is used as the raw material substrate, the problem of permeation of the etchant is generally more significant than a case in which the base oxide film is deposited on the substrate. Therefore, the present invention is suitably applied to a liquid crystal display substrate which may include the bonding SOI substrate having single crystal silicon TFTs.
In the connection structure between the signal lines and the short-circuit wiring, when the signal lines and the short-circuit wiring are formed in the same wiring layer, the signal lines and the short-circuit wiring may be integrally formed without the need for connection. On the other hand, when the signal lines and the short-circuit wiring are formed in different wiring layers, the signal lines and the short-circuit wiring may be electrically connected to each other through contact holes passing through the insulating film interposed therebetween.
A method of manufacturing a liquid crystal device substrate of an exemplary embodiment of the present invention is provided for manufacturing a liquid crystal device substrate which may constitute one of a pair of substrates of a liquid crystal device in which a liquid crystal is held between the pair of substrates, and which may include a substrate, a base oxide film provided on the substrate, a plurality of signal lines, and short-circuit wiring provided on the base oxide film for electrically connecting the plurality of signal lines during a manufacturing process. The method may include the step of forming, on the base insulating film, an etching stop layer which may include a film having resistance to etching of an oxide film formed on the short-circuit wiring, the step of forming the short-circuit wiring on the base insulating film so that the short-circuit wiring crosses the etching stop layer, the step of forming an insulating film to cover the short-circuit wiring, the step of forming a hole in the insulating film above the etching stop layer formation region for cutting the short-circuit wiring by etching in releasing the signal lines from a short-circuit state, the step of etching out the oxide film formed on the surface of the short-circuit wiring through the hole, and the step of cutting the short-circuit wiring through the hole.
Preferably, the etching stop layer is formed before the formation of the short-circuit wiring, and may include an arbitrary film used at positions other than the short-circuit wiring formation positions in the liquid crystal device substrate.
The method of manufacturing a liquid crystal device substrate of the present invention can easily manufacture the liquid crystal device substrate of the present invention, and can obtain the effect of preventing the occurrence of cracking and peeling of the insulating film accompanying the step of cutting the short-circuit wiring.
More specifically, the method of manufacturing a liquid crystal device substrate of an exemplary embodiment of the present invention is provided for manufacturing a liquid crystal device substrate which may constitute one of a pair of substrates of a liquid crystal device in which a liquid crystal is held between the pair of substrates, and which may include a substrate, a base oxide film provided on the substrate, a plurality of signal lines, a plurality of pixel electrodes respectively connected to the plurality of signal lines, short-circuit wiring provided on the base oxide film for electrically connecting the plurality of signal lines during a manufacturing process, and TFTs each including a silicon film as a semiconductor active film. The method may include: the step of patterning a silicon film on the base insulating film to form the semiconductor active films of the TFTs and form an etching stop layer having resistance to etching of a silicon oxide film, the step of forming a silicon oxide film on the remaining silicon film, the step of depositing a gate electrode material film for the TFTs over the entire surface and patterning it to form scanning lines which constitute the signal lines, gate electrodes of the TFTs, and the short-circuit wiring which crosses the etching stop layer, the step of introducing an impurity into the semiconductor active films of TFTs to form source and drain regions, the step of forming a first interlayer insulating film to cover the TFTs and the short-circuit wiring, the step of patterning the first interlayer insulating film to form source contact holes which pass through the first interlayer insulating film and reach the source regions of the TFTs, the step of depositing a conductive film and patterning it to form data lines which constitute the signal lines electrically connected to the source regions through the source contact holes and form terminals, the step of forming a second interlayer insulating film to cover the data lines and the terminals, the step of patterning the second interlayer insulating film and the first interlayer insulating film to form drain contact holes, which pass through both interlayer insulating films and reach the drain regions of the TFTs, and form holes in the etching stop layer forming regions for cutting the short-circuit wiring, the step of forming pixel electrodes electrically connected to the drain regions through the drain contact holes, the step of forming a mask pattern on the second internal insulating film and wit-etching the second interlayer insulating film to expose the surfaces of the terminals and removing a native oxide film formed on the short-circuit wiring through the holes, and the step of cutting the short-circuit wiring by etching through the holes.
Where each of the semiconductor active films of the TFTs and the silicon film, which constitutes the etching stop layer includes a single crystal silicon film, the bonding SOI substrate can be used as the raw material substrate.
In the method of manufacturing a liquid crystal device substrate of another exemplary embodiment of the present invention, the etching stop layer is formed at the same time as the semiconductor active films of the TFTs, and the short-circuit wiring is formed at the same time as the gate electrodes of the TFTs. Therefore, the semiconductor active films and the etching stop layer may include a silicon film, and the use of a polycrystalline silicon film as the gate electrode material for the TFTs causes the formation of the short-circuit wiring which may include the polycrystalline silicon film. Then, the source regions and the drain regions of the TFTs are formed, and the TFTs are covered with the first interlayer insulating film. However, the data lines connected to the source regions are formed at the same time as the formation of the terminals for connection to external wiring at the ends of various signal wires by using the same layer as the data lines.
Furthermore, the data lines and the terminals are coated with the second interlayer insulating film, and the drain contact holes are formed for connecting the pixel electrodes to the drain regions. However, by using this step, holes are formed above the short-circuit wiring. Although the pixel electrodes are then formed in the pixel region, in some cases, the native oxide film is formed on the surface of the short-circuit wiring, for example, which may include the polycrystalline silicon film, during the passage of this step. In some cases, the presence of the native oxide film hinders the short-circuit wiring from being sufficiently etched in the subsequent step of cutting the short-circuit wiring. Therefore, the step of removing the native oxide film on the surface of the short-circuit wiring is required before the cutting step. However, in the exemplary embodiments of the present invention, this step is performed at the same time as the step of forming the terminals. The method of the exemplary embodiments of the present invention does not have the problem of cracking the insulating film because of the presence of the etching stop layer. Finally, the short-circuit wiring can be cut by etching through the holes.
In this way, in the method of manufacturing a liquid crystal device substrate of the various exemplary embodiments of the present invention, various films are deposited, patterned, and etched in the same step, and thus the short-circuit wiring is formed and cut at the same time as the formation of the TFTs and the terminals, thereby preventing complication of the manufacturing process as compared with a case including no electrostatic measure (without forming the short-circuit wiring). Strictly, etching of the short-circuit wiring is, of course, added, but etching may be performed by using the mask pattern used in the step of exposing the terminals, without increasing the number of the photolithography steps. Therefore, an electrostatic measure can be carried out with less change in the time and labor required for the process, as compared with other manufacturing processes. In addition, the manufacturing method of the exemplary embodiments of the present invention may include the step of cutting the short-circuit wiring after the step of exposing the terminals nearest to the final step of the manufacturing process, and thus the short-circuit wiring functions in the most of the steps of the manufacturing process, thereby providing the effective electrostatic measure.
A liquid crystal device of the various exemplary embodiments of the present invention may include a liquid crystal held between a pair of substrates, wherein at least one of the pair of substrates may include the above-described exemplary embodiments of the liquid crystal device substrate of the present invention.
By using the liquid crystal device substrate of the exemplary embodiments of the present invention, a liquid crystal device exhibiting high image quality and high performance, and producing less display defect due to electrostatic damage or the like can be realized.
A projection liquid crystal display of various exemplary embodiments of the present invention may include the liquid crystal device of the exemplary embodiments of the present invention serving as a light valve, so that light emitted from a light source is modulated by the liquid crystal device. The modulated light is enlarged and projected on a projection screen by a projection optical device.
Particularly, a projection liquid crystal display has the tendency that display defects can easily be seen by the user because an image is enlarged and projected, but a projected image having good image quality and less defect due to electrostatic damage or the like can be obtained.
An electronic apparatus of various exemplary embodiments of the present invention may include the above-described exemplary embodiments of the liquid crystal display of the present invention.
By using the liquid crystal device of the various exemplary embodiments of the present invention, an electronic apparatus having less defect due to electrostatic damage or the like, and high image quality and high performance can be realized.